Shekhar Pramanick
61Patents
22h-index
34Co-inventors
80Inventor score
Filing activity: Nov 29, 1994 → Nov 12, 2002
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6144099A | Semiconductor metalization barrier | Electricity | 279 | Expired |
| US5617991A | Method for electrically conductive metal-to-metal bonding | Electricity | 258 | Expired |
| US6344410B1 | Manufacturing method for semiconductor metalization barrier | Electricity | 248 | Expired |
| US6380019B1 | Method of manufacturing a transistor with local insulator structure | Electricity | 138 | Expired |
| US6221724A | Method of fabricating an integrated circuit having punch-through suppression | Electricity | 130 | Expired |
| US6184112A | Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile | Electricity | 127 | Expired |
| US6670260B1 | Transistor with local insulator structure | Electricity | 122 | Expired |
| US6147000A | Method for forming low dielectric passivation of copper interconnects | Electricity | 106 | Expired |
| US6022808A | Copper interconnect methodology for enhanced electromigration resistance | Electricity | 74 | Expired |
| US6303505A | Copper interconnect with improved electromigration resistance | Electricity | 47 | Expired |
| US6060383A | Method for making multilayered coaxial interconnect structure | Electricity | 46 | Expired |
| US6214731A | Copper metalization with improved electromigration resistance | Electricity | 39 | Expired |
| US6054398A | Semiconductor interconnect barrier for fluorinated dielectrics | Electricity | 36 | Expired |
| US6660634B1 | Method of forming reliable capped copper interconnects | Emerging Cross-Sectional Technologies | 34 | Expired |
| US6239021A | Dual barrier and conductor deposition in a dual damascene process for semiconductors | Emerging Cross-Sectional Technologies | 32 | Expired |
| US6180469A | Low resistance salicide technology with reduced silicon consumption | Electricity | 32 | Expired |
| US6165894A | Method of reliably capping copper interconnects | Electricity | 31 | Expired |
| US5937315A | Self-aligned silicide gate technology for advanced submicron MOS devices | Electricity | 31 | Expired |
| US6117770A | Method for implanting semiconductor conductive layers | Electricity | 31 | Expired |
| US6492266B1 | Method of forming reliable capped copper interconnects | Emerging Cross-Sectional Technologies | 29 | Expired |
| US6211084A | Method of forming reliable copper interconnects | Electricity | 27 | Expired |
| US6734559B1 | Self-aligned semiconductor interconnect barrier and manufacturing method therefor | Electricity | 24 | Expired |
| US6127193A | Test structure used to measure metal bottom coverage in trenches and vias/contacts and method for creating the test structure | Electricity | 22 | Expired |
| US6143650A | Semiconductor interconnect interface processing by pulse laser anneal | Electricity | 22 | Expired |
| US6008098A | Ultra shallow junction formation using amorphous silicon layer | Electricity | 22 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.