Method of making a metal oxide semiconductor (MOS) transistor polysilicon gate with a size beyond photolithography limitation by using polysilicidation and selective etching
US5937319A · kind A · utility
21Cited by
7References
58Claims
0Family size
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Key dates
| Filing date | Oct 31, 1997 |
| Grant date | Aug 10, 1999 |
| Priority date | — |
| Expiry date | Oct 31, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28123
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a polysilicon gate 8 in a metal oxide semiconductor (MOS) transistor in an integrated circuit includes providing a metal layer 18, such as cobalt, on the sidewall 12 of the polysilicon gate 8, silicidizing the metal with the polysilicon in the polysilicon gate 8 to form a metal silicide sidewall 20, and removing the metal silicide sidewall 20 by etching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.