Sequencing of the recipe steps for the optimal low-k HDP-CVD processing
US5937323A · kind A · utility
861Cited by
19References
23Claims
0Family size
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Key dates
| Filing date | Jun 3, 1997 |
| Grant date | Aug 10, 1999 |
| Priority date | — |
| Expiry date | Jun 3, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02274
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A sequence of process steps forms a fluorinated silicon glass (FSG) layer on a substrate. This layer is much less likely to form a haze or bubbles in the layer, and is less likely to desorb water vapor during subsequent processing steps than other FSG layers. An undoped silicon glass (USG) liner protects the substrate from corrosive attack. The USG liner and FSG layers are deposited on a relatively hot wafer surface and can fill trenches on the substrate as narrow as 0.8 .mu.m with an aspect ratio of up to 4.5:1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.