Process for manufacturing a semiconductor package with bi-substrate die
US5946553A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 1995 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Sep 25, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/0723
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an interconnect for semiconductor devices is provided. The interconnect includes raised contact structures covered with a conductive layer and having penetrating projections for penetrating contacts for the semiconductor devices. In an illustrative embodiment, the interconnect can be used to form a bi-substrate die. An interconnect substrate for the bi-substrate die includes control and logic circuitry and a memory substrate for the bi-substrate die includes a memory array. The interconnect can also be used to establish an electrical connection to microscopic contacts formed on a conventional die. In addition, the interconnect can be formed with three dimensional micro structures for contacting the microscopic contacts. Still further, the interconnect can be formed as wafer interconnect for electrically contacting dice contained on a wafer or for stacking multiple wafers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.