Method for making shallow trench marks
US5963816A · kind A · utility
30Cited by
1References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1997 |
| Grant date | Oct 5, 1999 |
| Priority date | — |
| Expiry date | Dec 1, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The separate formation of alignment marks and manufacturing a semiconductor device comprising photolithographically printing circuit patterns is avoided by utilizing trenches formed when etching to form shallow isolation trenches, thereby increasing manufacturing throughput and reducing costs. Embodiments include utilizing alignment trenches having a depth of about 2,400.ANG. to less than about 4,000.ANG., e.g., 3,000.ANG., formed substantially simultaneously with forming isolation trenches having substantially the same depth as the alignment trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.