Semiconductor package and assembly for fabricating the same
US5977624A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jan 16, 1998 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | Jan 16, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip size semiconductor package with a light, thin, simple and compact structure having a reduced size of its semiconductor chip while having an increased number of pins and without degrading its functions. For the package, it is possible to use either the semiconductor chip having bond pads arranged on end portions of the chip or the semiconductor chip having bond pads arranged on the central portion of the chip. In either case, input/output terminals of the package are arranged in the form of an area array. Accordingly, when the package is mounted on an electronic appliance, its mounting area can be minimized, thereby achieving a compactness of the final product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.