Method for reducing defects in a semiconductor lithographic process
US5985497A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1998 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Feb 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/7065
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An arrangement for optimizing a lithographic process forms a pattern on a silicon wafer using a photocluster cell system to simulate an actual processing condition for a semiconductor product. The resist pattern is then inspected using a wafer inspection system. An in-line low voltage scanning electron microscope (SEM) system reviews and classifies defect types, enabling generation of an alternative processing specification. The alternative processing specification can then be tested by forming patterns on different wafers, and then performing split-series testing to analyze the patterns on the different wafers for comparison with the existing lithographic process and qualification for production.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.