Method of forming a via hole structure including CVD tungsten silicide barrier layer
US5985749A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1997 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Jun 25, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76843
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to integrated circuits and to via hole structures which include a tungsten silicide barrier layer and to methods of forming such via hole structures. In an exemplary embodiment, a metal layer is formed on a sidewall and a bottom surface of the via hole, a WSi.sub.x barrier layer is formed on the first metal layer by chemical vapor deposition and the via hole is subsequently filled with a metal. The tungsten silicide barrier layer effectively suppresses device degradation resulting from the release of gaseous species from the sidewall of the via hole during plug formation. Semiconductor devices can thus be fabricated which are immune or less susceptible to metal open failures due to incomplete via filling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.