LDD transistor using novel gate trim technique
US6013570A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 1998 |
| Grant date | Jan 11, 2000 |
| Priority date | — |
| Expiry date | Jul 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0221
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An ultra-large scale MOS integrated circuit semiconductor device is processed after the formation of the gate oxide and polysilicon layer by forming a forming a first mask layer over the polysilicon layer followed by a second mask layer over the first mask layer. The first mask layer and the second mask layer are patterned to form first gate mask and second gate mask respectively. The polysilicon gate is then formed by anisotropically etching the polysilicon layer. The second gate mask is then removed. The polysilicon gate is then etched isotropically to reduce its width using the gate oxide layer and the patterned first gate mask as hard masks. The first gate mask is then used as a mask for dopant implantation to form source and drain extensions which are spaced away from the edges of the polysilicon gate. Thereafter, the first gate mask is removed and a spacer is formed dopant implantation to form deep source and drain junctions. A higher temperature rapid thermal anneal then optimizes the source and drain extension junctions and junctions, and the spacer is removed. Since the source and drain extension junctions are spaced away from the edges of the polysilicon gate, the displac…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.