Patrick K. Cheung
14Patents
9h-index
20Co-inventors
64Inventor score
Filing activity: Jul 17, 1998 → May 18, 2007
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6787458B1 | Polymer memory device formed in via opening | Electricity | 38 | Expired |
| US6274443A | Simplified graded LDD transistor using controlled polysilicon gate profile | Electricity | 27 | Expired |
| US6013570A | LDD transistor using novel gate trim technique | Electricity | 25 | Expired |
| US6803267B1 | Silicon containing material for patterning polymeric memory element | Electricity | 25 | Expired |
| US7220985B2 | Self aligned memory element and wordline | Electricity | 21 | Expired |
| US6955939B1 | Memory element formation with photosensitive polymer dielectric | Emerging Cross-Sectional Technologies | 18 | Expired |
| US6191044A | Method for forming graded LDD transistor using controlled polysilicon gate profile | Electricity | 14 | Expired |
| US6287922A | Method for fabricating graded LDD transistor using controlled polysilicon gate profile | Emerging Cross-Sectional Technologies | 13 | Expired |
| US7015504B2 | Sidewall formation for high density polymer memory element array | Electricity | 13 | Expired |
| US6900488B1 | Multi-cell organic memory element and methods of operating and fabricating | Electricity | 7 | Expired |
| US6989563B1 | Flash memory cell with UV protective layer | Electricity | 5 | Expired |
| US6836398B1 | System and method of forming a passive layer by a CMP process | Electricity | 5 | Expired |
| US6350639B1 | Simplified graded LDD transistor using controlled polysilicon gate profile | Electricity | 3 | Expired |
| US7645632B2 | Self aligned memory element and wordline | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.