Marking Bad printed circuit boards for semiconductor packages
US6021563A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jun 25, 1997 |
| Grant date | Feb 8, 2000 |
| Priority date | — |
| Expiry date | Jun 25, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for marking poor quality printed circuit board units of a printed circuit board strip for ball grid array semiconductor packages wherein at least one degradation-indicating hole is at least partially formed in a poor quality printed circuit board unit of the strip at a region defined between an outer edge of the resin seal molding region of the unit and a cutting line formed on the printed circuit board strip to separate the unit from the strip. Even when a plurality of printed circuit board strips are packed in a vacuum under the condition in which they are stacked, there is no phenomenon that those strips in the pack are permanently deformed, for example, permanently bent. Also, there is no phenomenon that melt resin is leaked from the mold, thereby causing it to be bled out onto the upper surface of the printed circuit board strip. Since no paint is used to mark poor quality printed circuit board units, there is no problem associated with the use of the paint such as a contamination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.