Method of planarize and improve the effectiveness of the stop layer
US6025272A · kind A · utility
2Cited by
4References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1998 |
| Grant date | Feb 15, 2000 |
| Priority date | — |
| Expiry date | Sep 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device including a step of filling crevices or non-level regions formed during the manufacture of the semiconductor device with a spin-on dielectric material. The spin-on dielectric material prevents conductive material from filling the crevices and causing the device to fail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.