Thomas C. Scholer
13Patents
11h-index
2Co-inventors
54Inventor score
Filing activity: Feb 27, 1998 → May 1, 2002
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6025259A | Dual damascene process using high selectivity boundary layers | Electricity | 52 | Expired |
| US6239008A | Method of making a density multiplier for semiconductor device manufacturing | Electricity | 46 | Expired |
| US6448606B1 | Semiconductor with increased gate coupling coefficient | Electricity | 34 | Expired |
| US6287968A | Method of defining copper seed layer for selective electroless plating processing | Electricity | 31 | Expired |
| US6091138A | Multi-chip packaging using bump technology | Electricity | 23 | Expired |
| US5985753A | Method to manufacture dual damascene using a phantom implant mask | Electricity | 21 | Expired |
| US6103616A | Method to manufacture dual damascene structures by utilizing short resist spacers | Electricity | 20 | Expired |
| US6100593A | Multiple chip hybrid package using bump technology | Electricity | 18 | Expired |
| US6524916B1 | Controlled gate length and gate profile semiconductor device and manufacturing method therefor | Electricity | 15 | Expired |
| US6433371B1 | Controlled gate length and gate profile semiconductor device | Electricity | 13 | Expired |
| US6107204A | Method to manufacture multiple damascene by utilizing etch selectivity | Electricity | 12 | Expired |
| US6133140A | Method of manufacturing dual damascene utilizing anisotropic and isotropic properties | Electricity | 4 | Expired |
| US6025272A | Method of planarize and improve the effectiveness of the stop layer | Electricity | 2 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.