Use of pulsed-DC wafer bias for filling vias/trenches with metal in HDP physical vapor deposition
US6051114A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1997 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Jun 23, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method and apparatus for preferential PVD conductor fill in an integrated circuit structure. The present invention utilizes a high density plasma for sputter deposition of a conductive layer on a patterned substrate, and a pulsed DC power source capacitively coupled to the substrate to generate an ion current at the surface of the substrate. The ion current prevents sticking of the deposited material to the field areas of the patterned substrate, or etches deposited material from the field areas to eliminate crowning or cusping problems associated with deposition of a conductive material in a trench, hole or via formed on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.