Forming local interconnects in integrated circuits
US6051881A · kind A · utility
17Cited by
7References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 1997 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Dec 5, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/204
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and the resulting device to permit the formation of minimal insulating space between polysilicon gates by forming an insulating layer over the polysilicon gates and protecting selected ones of the gates and the insulating layer with an etch barrier so that the opening for local interconnect metallization can be misaligned and the selected gates will be protected by its etch barrier and not be exposed to the opening. Further, local interconnect conductive material can pass over a gate or unrelated resistor without shorting the gate/resistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.