Integrated etch process for polysilicon/metal gate
US6060376A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 1998 |
| Grant date | May 9, 2000 |
| Priority date | — |
| Expiry date | Jan 12, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate region of a transistor is prepared for receiving a deposit of metal. A chemical mechanical polishing process is performed to reduce thickness of an insulation layer above the gate region. At the end of the chemical mechanical polishing process, a portion of the insulating layer remains above the gate region. An etch process is performed to remove the portion of the insulating layer remaining above the gate region. The etch process also removes a portion of polysilicon within the gate region and removes a top portion of spacers on either side of the gate region. A polysilicon selective etch-back is performed to remove an additional portion of the polysilicon within the gate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.