Semiconductor fabrication employing a conformal layer of CVD deposited TiN at the periphery of an interconnect
US6060389A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 1998 |
| Grant date | May 9, 2000 |
| Priority date | — |
| Expiry date | May 11, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76895
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a local interconnect coupled to an active area of a semiconductor substrate is provided. The method comprises etching a local interconnect trench into an interlevel dielectric horizontally above the substrate. A titanium layer may be deposited across the semiconductor topography. A TiN diffusion layer is advantageously CVD deposited across the exposed surfaces of the titanium layer. A plasma containing N.sub.2 and H.sub.2 ions is used to bombard the surface of the TiN layer. The resulting TiN layer is conformal and has a low resistivity. A tungsten fill material is then deposited upon the TiN layer to a level above the dielectric. The tungsten adheres well to the TiN layer and is substantially free of voids. The TiN and the tungsten may be removed down to level commensurate with the surface of the dielectric. In this manner a local interconnect is formed electrically coupled to the active area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.