Method and apparatus for performing partial unscan and near full scan within design for test applications
US6067650A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 1997 |
| Grant date | May 23, 2000 |
| Priority date | — |
| Expiry date | Dec 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318586
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A computer implemented process and system for effectively determining a set of sequential cells with a integrated circuit design that can be scan replaced (e.g. for design for test applications) to offer significant testability while still maintaining specified optimization (e.g., area and/or timing) constraints that are applicable to the design. The novel system selects sequential cells for scan replacement that offer best testability contribution while not selecting sequential cells for scan replacement that do not offer much testability contribution and/or are part of most critical paths within the design. The novel system is composed of a subtractive method and an additive method. The subtractive method inputs a fully scan replaced netlist (e.g., the sequential cells are scan replaced) that does not meet determined optimization constraints. The novel subtractive system unscans selected cells until the area and/or timing constraints are met. A flag indicates whether nor not timing is considered. Selection for unscanning is based on a testability cell list (TCL) that ranks cells by their degree of testability contribution; those cells with low degrees of testability are unscanned…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.