Pipelined processor with microcontrol of register translation hardware
US6073231A · kind A · utility
41Cited by
11References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 17, 1997 |
| Grant date | Jun 6, 2000 |
| Priority date | — |
| Expiry date | Mar 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/384
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor comprises one or more instruction pipelines having a plurality of stages for processing a stream of instructions, with one or more of said instructions referencing a set of logical registers. A plurality of physical registers are allocated to store data associated with the logical registers by register translation circuitry. The register translation circuitry is selectively controlled by the microcode or by hardware signals generated by one or more of the stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.