Semiconductor device having a multi-layer metal interconnect structure
US6075293A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1999 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Mar 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-level metal interconnect structure in a semiconductor device includes a plurality of overlying metal layers separated by ILD layers and electrically connected by filled vias in the ILD layers. Each metal layer includes a relatively thick antireflective layer for improved electromigration resistance. Each metal layer also includes a metal lining layer and a metal interconnect layer overlying the metal lining layer. Enhanced electromigration resistance is obtained by forming the antireflective layer to a thickness of no less than the thickness of the metal lining layer. In a preferred embodiment of the invention, the antireflective layer has a thickness of about 1000 angstroms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.