Method to form an alignment mark
US6080659A · kind A · utility
12Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1998 |
| Grant date | Jun 27, 2000 |
| Priority date | — |
| Expiry date | Nov 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method to form a better quality of an alignment pattern includes several steps, first starts from forming a polysilicon layer on a semiconductor substrate. Next, most of a central portion of the polysilicon layer is removed to expose the substrate. Then, an oxide layer is formed over the substrate and is patterned to form an opening, which exposes the substrate. A W layer is deposited over the substrate and is planarized by WCMP process to form a W plug inside the opening. A metal layer is formed over the substrate. The alignment mark pattern is formed on the metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.