Transistor having a metal silicide self-aligned to the gate
US6084280A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1998 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Oct 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor having a source/drain metal silicide in close proximity to the channel region may be formed according to the following process. A masking structure is formed upon a semiconductor substrate, and a metal is deposited self-aligned to sidewall surfaces of the masking structure. The metal is then annealed to form a metal silicide. Following formation of lightly doped drain impurity areas self-aligned to the sidewall surfaces of the masking structure, spacers may be formed adjacent the sidewall surfaces and source and drain impurity areas may be formed self-aligned to sidewall surfaces of the spacers. Fill structures are then formed adjacent the spacers and the masking structure is removed to form an opening between the spacers. A gate dielectric is formed upon the exposed upper surface of the semiconductor substrate within the opening, and a gate conductor is formed within the opening. According to one embodiment, the fill structures are removed and an interlevel dielectric is formed upon the transistor. In an alternative embodiment, the fill structures include a dielectric material and are retained as interlevel dielectrics. In a further embodiment, the fill structures inc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.