System and method for selectively controlling fetching and prefetching of data to a processor
US6085291A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1995 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Nov 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Within a data processing system implementing primary and secondary caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. Prefetching may be performed on cache misses or hits. Cache misses on successive cache lines may allocate a stream of cache lines to the stream buffers. Control circuitry, coupled to a stream filter circuit, selectively controls fetching and prefetching of data from system memory to the primary and secondary caches associated with a processor and to a stream buffer circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.