Multi-chip packaging using bump technology
US6091138A · kind A · utility
23Cited by
7References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1998 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Feb 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16195
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multichip integrated semiconductor device having a portion of a first chip bonded to electrical leads in a package using a flip chip technology such as solder bump technology and a second chip bonded to a second portion of the first chip using a flip chip technology such as solder bump technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.