Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM
US6091263A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 1997 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Dec 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A field programmable gate array (FPGA) which includes first and second arrays of configurable logic blocks, and first and second configuration cache memories coupled to the first and second arrays of configurable logic blocks, respectively. The first configuration cache memory array can either store values for reconfiguring the first array of configurable logic blocks, or operate as a RAM. Similarly, the second configuration cache array can either store values for reconfiguring the second array of configurable logic blocks, or operate as a RAM. The first configuration cache memory array and the second configuration cache memory array are independently controlled, such that partial reconfiguration of the FPGA can be accomplished. In addition, the second configuration cache memory array can store values for reconfiguring the first (rather than the second) array of configurable logic blocks, thereby providing a second-level reconfiguration cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.