High integrity borderless vias with HSQ gap filled patterned conductive layers
US6093635A · kind A · utility
16Cited by
8References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1997 |
| Grant date | Jul 25, 2000 |
| Priority date | — |
| Expiry date | Dec 18, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/958
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Borderless vias are formed in electrical connection with a lower metal feature of a metal pattern gap filled with HSQ. Heat treatment in an inert atmosphere is conducted before filling the through-hole to outgas water absorbed during solvent cleaning of the through-hole, thereby reducing via void formation and improving via integrity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.