Computer processor with a replay system having a plurality of checkers
US6094717A · kind A · utility
27Cited by
7References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1998 |
| Grant date | Jul 25, 2000 |
| Priority date | — |
| Expiry date | Jul 31, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer processor includes a multiplexer having a first input, a second input, a third input, and an output. The processor further includes a scheduler coupled to the multiplexer first input, an execution unit coupled to the multiplexer output, and a replay system that has an input coupled to the multiplexer output. The replay system includes a first checker coupled to the replay system input and the second multiplexer input, and a second checker coupled to the first checker and the third multiplexer input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.