Test arrangement for memory devices using a dynamic row for creating test data
US6094734A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 1997 |
| Grant date | Jul 25, 2000 |
| Priority date | — |
| Expiry date | Aug 22, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test arrangement for a memory device wherein the equilibration voltage DVC2 is adjusted up or down relative to a nominal value and coupled to one of the bitlines of the paired bitlines of the memory array, while the equilibrating circuit is held disabled, and then the sense amplifiers are used to pull the bitlines to logic 1 and logic 0 levels initializing the bitlines to test data. Appropriate word lines are fired to copy the test data to some or all of the other rows of the memory array, allowing memory tests to be conducted. In another embodiment, a fixed voltage is applied to one of the bitlines of individual bitlines pairs and the sense amplifiers are used to pull the paired bitlines to the correct voltage. In a further embodiment, fixed voltages Vcc and ground are applied to the bitlines of each bitline pair with the sense amplifier being held disabled. The test arrangement can be implemented as a self-test feature for the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.