Method of fabricating a semiconductor device having polysilicon line with extended silicide layer
US6096643A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1998 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Oct 1, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76895
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and fabrication process are provided in which a polysilicon line is disposed on a substrate of the semiconductor device. The polysilicon line may, for example, be a gate electrode. A dielectric layer is disposed adjacent the polysilicon line and an extended silicide layer is formed over the polysilicon line. The extended silicide layer may be formed by forming a patterned metal layer over the polysilicon line, forming a polysilicon layer over the patterned metal layer, and reacting the patterned metal layer with the polysilicon layer to form the extended silicide layer over the polysilicon line. The device may further include a second polysilicon line, such as a gate electrode, and the silicide layer may extend over the top of the second polysilicon line and interconnects the two polysilicon lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.