Low dielectric constant coating of conductive material in a damascene process for semiconductors
US6100181A · kind A · utility
19Cited by
2References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 5, 1999 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | May 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing an integrated circuit using damascene processes is provided in which planar surfaces subjected to chemical-mechanical polishing are protected by a protective low dielectric constant coating. The coatings are of organic silicon materials which are spun on and baked in preparation of the deposition of subsequent dielectric layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.