Multiple chip hybrid package using bump technology
US6100593A · kind A · utility
18Cited by
3References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1998 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Feb 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16195
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multiple chip hybrid package using bump technology having multiple chips electrically connected using a flip chip technology such as solder bump technology. Portion of at least one chip is electrically connected to electrical leads connecting terminals inside the package to pins outside the package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.