Hierarchical scan architecture for design for test applications
US6106568A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 1999 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Jun 3, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31704
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method for architecting design for test circuitry (e.g., scan architecting) within an integrated circuit design having subdesigns (e.g., modules). The novel system contains a default operational mode (no user specification) and an operational mode based on user specifications; within either mode, the system recognizes and allows definition of subdesign scan chains which can be linked together alone or with other scan elements to architect complex scan chains (e.g., top level scan chains). The system includes specification, analysis, synthesis and reporting processes which can be used in an IC design having a hierarchical structure including modules. The specification process accesses a design database and a script file and allows a user to define global scan properties (scan style, number of chains, etc.), properties of a particular scan chain (membership, name, etc.), test signals (scan-in, scan-out, scan-enable, etc.), complex elements used as part of a scan chain without requiring scan replacement, wires and latches forming connections between scan elements; this information is associated with the selected design database. Analysis reads the design database and perf…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.