Controlled linewidth reduction during gate pattern formation using an SiON BARC
US6107172A · kind A · utility
31Cited by
13References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 1, 1997 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Aug 1, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/952
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate is formed by creating a wafer stack, that includes a gate conductive layer over a substrate layer, depositing a SiO.sub.x N.sub.y layer over the conductive layer to act as a bottom anti-reflective coating (BARC), and forming a resist mask on the SiO.sub.x N.sub.y layer. Next, the resist mask is isotropically etched to further reduce the critical dimensions of the gate pattern formed therein, and then the underlying BARC and wafer stack are etched to form a gate out of the conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.