Method to manufacture multiple damascene by utilizing etch selectivity
US6107204A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1998 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Oct 2, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device having multiple layers of interconnects that are filled in a single conductive material filling step. Two layers of interlayer dielectric separated by an etch stop layer are formed over a layer including metal structures in contact with electrodes of active devices formed in and on a semiconductor substrate. A layer of photoresist is formed on a second etch stop layer formed on the upper layer of interlayer dielectric. The layer of photoresist is patterned and etched. Masking and etching processes form openings in the first and second layers of interlayer dielectric including openings to the metal structures. The openings are filled in a single conductive material filling step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.