Optimum buffer placement for noise avoidance
US6117182A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1998 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Jun 12, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for optimal insertion of buffers into an integrated circuit design. A model representative of a plurality of circuits is created where each circuit has a receiving node coupled to a conductor and a source. A receiving node is selected from the modeled plurality of circuits and circuit noise is calculated for the selected receiving node utilizing the circuit model. If the calculated circuit noise exceeds an acceptable value an optimum distance is computed from the receiving node on the conductor for buffer insertion. In a multi-sink circuit merging of the noise calculation for the two receiving circuits must be accomplished. If an intersection of conductors exists between the receiving node and the optimum distance a set of candidate buffer locations is generated. The method then prunes inferior solutions to provide an optimal insertion of buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.