Polishing method for semiconductor wafer and polishing pad used therein
US6120353A · kind A · utility
22Cited by
13References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 12, 1999 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Feb 12, 2019 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB24B37/24
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
In a polishing method for a semiconductor wafer in which polishing slurry is interposed between the semiconductor wafer and a polishing pad and the semiconductor wafer is mirror-polished by a polishing step for planarization, when polishing is conducted using a suede-like foam urethane resin polishing pad having physical properties of low compressibility lower than 9 % and high pore density equal to or higher than about 150 pores/cm.sup.2 as the polishing pad used in the polishing step, a mirror silicon wafer with good surface roughness of 50 bits in haze can be manufactured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.