Patent · US Expired

Device improvement by source to drain resistance lowering through undersilicidation

US6133124A · kind A · utility

24Cited by

10References

36Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Manfred Horstmann · Dresden, DE
Karsten Wieczorek · Dresden, DE
Frederick N. Hause · Austin, US

Key dates

Filing date	Feb 5, 1999
Grant date	Oct 17, 2000
Priority date	—
Expiry date	Feb 5, 2019

Classification

Technology area (CPC H)Electricity
CPC primaryH10D30/0212
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Various methods of fabricating a silicide layer, and devices incorporating the same are provided. In one aspect, a method of fabricating a silicide layer on a substrate is provided. The method includes the steps of damaging the crystal structure of a portion of the substrate positioned beneath the spacer and depositing a layer of metal on the substrate. The metal layer and the substrate are heated to react the metal with the substrate and form the silicide layer, whereby a portion of the silicide layer extends laterally beneath the spacer. Any unreacted metal is removed. The method enables fabrication of silicide layers with substantial lateral encroachment into LDD structures, resulting in lower possible source-to-drain resistance and enhanced performance for transistors.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.