Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer
US6137126A · kind A · utility
8Cited by
5References
10Claims
0Family size
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Key dates
| Filing date | Aug 17, 1999 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Aug 17, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The capacitance between a gate electrode of a transistor and local interconnect is reduced by employing SiC sidewall spacers on the side surfaces of the gate electrode when forming the source/drain regions with shallow extensions. Embodiments include forming SiC sidewall spacers at a width of about 500 .ANG. to about 800 .ANG. having a dielectric constant of less than about 3.2, depositing a silicon oxide inter-dielectric layer, and forming the local interconnect through the inter-dielectric layer. The resulting composite dielectric constant between the gate electrode and local interconnect is about 4.2 to about 4.7.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.