Low temperature integrated via and trench fill process and apparatus
US6139697A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 1997 |
| Grant date | Oct 31, 2000 |
| Priority date | — |
| Expiry date | Jan 31, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28556
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates generally to an improved process for providing complete via fill on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer, such as CVD Al or CVD Cu, is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD Cu. Next, a PVD Cu is deposited onto the previously formed CVD Cu layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD Cu layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Cu layer. The via fill process of the present invention is also successful with air-exposure between the CVD Cu and PVD Cu steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.