Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol
US6141734A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1998 |
| Grant date | Oct 31, 2000 |
| Priority date | — |
| Expiry date | Feb 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for implementing load-locked and store-conditional instruction primitives by using a local cache for information about exclusive ownership. The valid bit in particular provides information to properly execute load-locked and store-conditional instructions without the need for lock flag or local lock address registers for each individual locked address. Integrity of locked data is accomplished by insuring that load-locked and store-conditional instructions are processed in order, that no internal agents can evict blocks from a local cache as a side effect as their processing, that external agents update the context of cache memories first using invalidating probe commands, and that only non-speculative instructions are permitted to generate external commands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.