Barrier layer decreases nitrogen contamination of peripheral gate regions during tunnel oxide nitridation

US6143608A · kind A · utility

Assignees

• Advanced Micro Devices, Inc. · US
• FUJITSU LIMITED · JP

Inventors

• Yue-Song He · San Jose, US
• Masaaki Higashitani · Cupertino, US
• Hao Fang · Cupertino, US
• Narbeh Derhacobian · Belmont, US
• Bill Douglas Cox · Palo Alto, US
• Kent Kuohua Chang · Cupertino, US
• Kelwin Ko · San Jose, US
• Maria Chow-Chan · San Jose, US

Key dates

• Filing date: Mar 31, 1999
• Grant date: Nov 7, 2000
• Expiry date: Mar 31, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/44

Abstract

This invention describes methods for producing gate oxide regions in periphery regions of semiconductor chips, wherein the gate oxide regions have improved electrical properties. The methods involve the deposition of a barrier layer over the periphery of the semiconductor chip to prevent the introduction of contaminating nitrogen atoms into the periphery during a nitridation step in the core region of the semiconductor chip. By preventing the contamination of the gate areas of the periphery, the gate oxide regions so produced have increased breakdown voltages and increased reliability. This invention describes methods for etching the barrier layers used to protect the periphery from tunnel oxide nitridation. Semiconductor devices made with the methods of this invention have longer expected lifetimes and can be manufactured with higher device density.