Method of reducing metal voidings in 0.25 .mu.m AL interconnect
US6143672A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 1998 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | May 22, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76801
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention relates to a method of depositing a dielectric layer over a stacked interconnect structure, involving the steps of: providing a substrate having at least one stacked interconnect structure comprising at least one of an aluminum layer and an aluminum alloy layer; depositing the dielectric layer over the stacked interconnect structure PA1 under a pressure from about 1 mTorr to about 6 mTorr, an O.sub.2 flow rate from about 110 sccm to about 130 sccm and a silane flow rate from about 52 sccm to about 60 sccm at a bias power from about 2500 W to about 3100 W, PA1 under a pressure from about 2 Torr to about 2.8 Torr, an N.sub.2 flow rate from about 7 l to about 11.5 l, an N.sub.2 O flow rate from about 1 l to about 2 l and a silane flow rate from about 250 sccm to about 300 sccm at a power from about 900 W to about 1300 W at a temperature from about 300.degree. C. to about 350.degree. C., or PA1 under a pressure from about 2 Torr to about 2.8 Torr, an N.sub.2 flow rate from about 7 l to about 11.5 l, an N.sub.2 O flow rate from about 1 l to about 2 l and a silane flow rate from about 80 sccm to about 120 sccm at a power from about 900 W to about …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.