Semiconductor device having self-aligned asymmetric source/drain regions and method of fabrication thereof
US6146952A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1998 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | Oct 1, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and manufacturing method is provided in which asymmetric source/drain regions are formed using a self aligning implant mask. A gate electrode is formed on a substrate and a dielectric layer is formed over the substrate and adjacent the gate electrode. A masking layer is formed over the dielectric layer and the gate electrode and selectively removed to form an implant mask. The implant mask extends further over a first side of the gate electrode than a second side of the gate electrode. Using the implant mask for alignment, a dopant is implanted into the active regions of the substrate adjacent the gate electrode to form a first heavily-doped region adjacent the first side of the gate electrode and second heavily-doped region adjacent the second side of the gate electrode. The first heavily-doped region is spaced further from the gate electrode than the second heavily-doped region. Contacts may be formed to the masking layer or a silicide layer formed from the masking layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.