Minimizing transistor size in integrated circuits
US6146954A · kind A · utility
11Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 21, 1998 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | Jul 21, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal insulating space between polysilicon gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET. A portion of an insulating layer between the source and drain is removed prior to forming the gate. Preferably, an etch stop layer on the semiconductor substrate underlying the insulating layer is used in the method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.