Memory cell having a vertical transistor with buried source/drain and dual gates

US6150687A · kind A · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Wendell P. Noble · Colchester, US
• Leonard Forbes · Corvallis, US
• Kie Y. Ahn · Chappaqua, US

Key dates

• Filing date: Jul 8, 1997
• Grant date: Nov 21, 2000
• Expiry date: Jul 8, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/488

Abstract

An integrated circuit and fabrication method includes a memory cell for a dynamic random access memory (DRAM). Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried first and second gates are provided for each access transistor on opposing sides of the pillars. Buried word lines extend in trenches orthogonal to the bit lines. The buried word lines interconnect ones of the first and second gates. In one embodiment, unitary gates are interposed and shared between adjacent pillars for gating the transistors therein. In another embodiment, separate split gates are interposed between and provided to the adjacent pillars for separately gating the transistors therein. In one embodiment, the memory cell has a surface area that is approximately 4 F.sup.2, where F is a minimum feature size. Bulk-semiconductor and semiconductor-on-insulator (SOI) embodiments are provided.