Method for fabricating a dual material gate of a short channel field effect transistor
US6153534A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 1999 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Jul 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dual material gate is effectively fabricated for a field effect transistor having a short channel length of submicron and nanometer dimensions such that disadvantageous short channel effects are minimized. Generally, the method of the present invention includes a step of forming a first material gate portion on a gate dielectric. The first material gate portion has a source side and a drain side, and an aspect of the present invention further includes the step of depositing a spacer dielectric layer on the source side and the drain side of the first material gate portion. An aspect of the present invention also includes the step of implanting heavy ions into the spacer dielectric layer at an angle such that the spacer dielectric layer at the drain side of the first material gate portion is substantially not implanted with the heavy ions. The spacer dielectric layer is then selectively etched such that any portion of the spacer dielectric layer that is implanted with the heavy ions is etched. Thus, the spacer dielectric layer on the drain side of the first material gate portion is not etched, but the spacer dielectric layer on the source side of the first material gate portion is …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.