Method of fabricating vertical FET with sidewall gate electrode

US6156611A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Ellen Lan · Chandler, US
• Jenn Hwa Huang · Chandler, US
• Kurt Eisenbeiser · Tempe, US
• Yang Wang · Chandler, US

Key dates

• Filing date: Jul 20, 1998
• Grant date: Dec 5, 2000
• Expiry date: Jul 20, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/85

Abstract

A vertical FET is fabricated by etching through a contact layer into a drift layer on a compound semiconductor substrate to form a plurality of mesas, each mesa having an upper surface and each adjacent pair of mesas defining therebetween a trench with sidewalls and a bottom. A conductive layer is conformally deposited over the plurality of mesas and the trenches and anisotropically etched to form contacts on the sidewalls of the trenches and depositing source contacts on the upper surfaces of the mesas and a drain contact on a reverse side of the substrate.