Multi state sensing of NAND memory cells by applying reverse-bias voltage
US6166951A · kind A · utility
8Cited by
6References
7Claims
0Family size
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Key dates
| Filing date | Aug 6, 1999 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Aug 6, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for sensing multi states of a NAND memory cell by applying reverse bias voltage at a constant gate voltage, preferably zero volts, generating a memory cell current in response to the applied reverse P well bias, and sensing the memory cell state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.