Method for detecting or preparing intercell defects in more than one array of a memory device
US6167541A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 1998 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Mar 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of testing a memory device having two arrays of memory cells arranged in rows and columns. Sense amplifiers for respective columns are shared by the arrays, with the sense amplifiers being selectively coupled to the digit lines of respective columns in each array by respective isolation transistors. Cells of the memory array are tested by first writing known data bits to each of the cells. The isolation transistors for the first array are then turned on, and the isolation transistors for the second array are turned off. Predetermined voltages are coupled to the sense amplifiers through the digit lines of the first array by activating a row in the first array. A plurality of rows in the first array are then activated to couple the memory cells in each activated row to respective digit lines. The sense amplifiers are then coupled to respective digit lines in the second array by turning on the isolation transistors for the second array. A plurality of rows in the second array are then activated to couple the memory cells in each activated row to respective digit lines of the second array. The rows in the first and second arrays remain activated for a testing interval of suffi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.