Electron bean curing of low-k dielectrics in integrated circuits
US6169039A · kind A · utility
20Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1998 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | Nov 6, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit and a method of forming an integrated circuit is described. The integrated circuit includes a silicon substrate, a dielectric stack formed on the silicon substrate, and conductive metal lines overlying the silicon substrate. A first layer of low-k dielectric material overlies the at least one conductive metal line, and a second layer of low-k dielectric material overlies the first layer of low-k dielectric material. The first layer of low-k dielectric material is electron beam (E-beam) cured and the second layer of low-k dielectric material is thermally cured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.